Semiconductor chip having gettering layer, and method for manufacturing the same

ABSTRACT

In a semiconductor chip A wherein an element layer  2  having transistors and the like is formed on the front face, and the back face is joined to an underlying member, such as a package substrate, the thickness T is made 100 μm or less, and thereafter, a gettering layer  3  is formed on the back face of the semiconductor chip A. The gettering layer  3  is formed, for example, by polishing the back face of said semiconductor chip A using a polishing machine. Thereby, the yield of devices can be improved in the step for assembling the package.

CROSS-REFERENCE TO RELATED APPLICATION

This application is a divisional of U.S. application Ser. No.11/190,011, filed Jul. 27, 2005, the entire contents of which areincorporated herein by reference and is based upon and claims thebenefit of priority from prior Japanese Patent Application No.2004-220319, filed Jul. 28, 2004.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a semiconductor chip having a getteringlayer for removing impurities such as heavy metals, and to a method formanufacturing the same.

2. Description of the Related Art

In the manufacture of semiconductor devices, heavy-metal contaminationdue to copper and nickel, and the like leads to the destruction of gateinsulation films or the deterioration of element reliability, and is oneof causes to lower the yield of devices. The heavy-metal contaminationoccurs not only in the process for forming an element layer includingtransistors or the like on the surface of a wafer (first-half process),but also in the process for dicing the wafer and assembling thesemiconductor chips into a package (second-half process).

In order to prevent heavy-metal contamination, it is effective that agettering layer for removing (gettering) heavy metals is previouslyformed in the part of a wafer or a semiconductor chip (for example,refer to Japanese Patent Laid-Open No. 2001-250957, or Japanese PatentLaid-Open No. 56-56660).

When a package having a structure wherein a plurality of semiconductorchips are laminated, such as a multi-chip package (MCP), is used, thethickness of each semiconductor chip must be thinned in the second-halfprocess in order to raise the integration degree of the device.

By doing this, since the gettering layer formed inside or on the backface of the wafer in the first-half process is lost or thinned, therehave been problems wherein the element layer is contaminated by heavymetals in the second-half process, and the yield of devices are lowereddue to the defect of the gate insulation film.

SUMMARY OF THE INVENTION

The present invention has been devised to solve the above-describedproblems, and the object of the present invention is to provide asemiconductor chip having a gettering layer formed on the back face ofthe semiconductor chip for gettering heavy metals in the second-halfprocess, and a method for manufacturing such a semiconductor chip.

The above object is achieved by a semiconductor chip wherein an elementlayer is formed on the front face, and the back face is joined to anunderlying member, wherein a gettering layer is formed on said backface.

The above object is achieved by a method for manufacturing asemiconductor chip, wherein a gettering layer is formed on the back faceof a semiconductor chip by mechanically grinding the back face of saidsemiconductor chip using a silica material to form a damaged layer.

Other objects and further features of the present invention will beapparent from the following detailed description.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a sectional view of a semiconductor chip of the firstembodiment;

FIG. 2 is a sectional view of a semiconductor chip of the firstembodiment;

FIG. 3 is a micrograph of the back face of a semiconductor chip of thefirst embodiment;

FIG. 4 is a sectional view of a semiconductor chip of the secondembodiment;

FIG. 5 is a sectional view of a semiconductor chip of the thirdembodiment;

FIG. 6 is a sectional view of a wafer of the fourth embodiment;

FIGS. 7A and 7B are micrographs of a wafer of the fourth embodiment;

FIGS. 8A and 8B are micrographs of a wafer of the fourth embodiment; and

FIG. 9 is a sectional view of an MCP of the fifth embodiment.

BEST MODE FOR CARRYING OUT THE INVENTION

The manufacture of a semiconductor device is completed through steps forforming an element layer having transistors and the like on the frontface of a wafer and for performing electrical measurements (hereafter,these steps will be collectively referred to as the “first-halfprocess”); and steps for cutting semiconductor chips out of the wafer bydicing, and for assembling them into a package (hereafter, these stepswill be collectively referred to as the “second-half process”). Althoughthere are various types of packages, a multi-chip package (hereafterreferred to as “MCP”) formed by laminating a plurality of semiconductorchips is widely used for raising the integration degree of the device.

The embodiments of the present invention will be described belowreferring to the drawings. In the drawings, the same or correspondingparts will be denoted by the same reference numerals, and thedescription thereof will be simplified or omitted.

First Embodiment

In the first embodiment, there will be described a semiconductor chip,wherein an element layer having transistors and the like is formed onthe front face, and the back face is joined to an underlying member suchas an MCP substrate, wherein a gettering layer is formed on the backface; and a method for the manufacture thereof.

First, although not shown in the drawing, in the first-half process, anelement layer (2 to 3 μm) having transistors and the like is formed onthe front face of a wafer of a thickness of 700 to 750 μm, andelectrical measurements, such as G/W (good chip/wafer), are performed.

Next, the back face of the wafer (the surface opposite to the surface onwhich the element layer has been formed) is ground so that the thicknessof the wafer becomes 100 μm or less, for example, about 90 μm. Thereby,the thickness of a semiconductor chip subsequently formed can be relatedto the MCP.

Then, the semiconductor chip is cut out of the wafer by dicing. At thistime, the thickness of the semiconductor chip is about 90 μm.

FIG. 1 is a sectional view of a semiconductor chip A cut out of thewafer by dicing in the second-half process. The entire thickness T ofthe semiconductor chip A is about 90 μm. An element layer 2 havingtransistors and the like is formed on the front face of thesemiconductor substrate 1, and a gettering layer 3 for trapping heavymetals is formed on the back face of the semiconductor chip A. Thegettering layer 3 can be a thin film consisting of a polycrystallinesilicon film or a silicon nitride film, as well as a damaged layerformed by mechanical polishing, grinding or ion implantation.

In the semiconductor chip A wherein the element layer 2 havingtransistors and the like was formed on the front face, a gettering layer3 was formed on the back face of the semiconductor chip A which the backface is joined to an underlying member such as an MCP substrate.Thereby, heavy metals can be gettered in the second-half process.

Thereafter, a plurality of semiconductor chips A (not shown) areassembled into an MCP. At this time, since the thickness of asemiconductor chip A was 100 μm or less, the semiconductor chip A wasrelated to the MCP, and the total thickness of the package could bethinned. Thereby, the integration degree of the device can be raised.

Next, as an example of forming the gettering layer 3 shown in FIG. 1, anexample of forming a damaged layer on the back face of a semiconductorchip A will be shown.

The back face of a semiconductor chip A is mechanically polished using,for example, abrasive grains of a diameter of several microns consistingof a silica material containing silicon dioxide (SiO₂) as a majorcomponent, to form grooves 3 b of a depth of 2 to 3 μm on the back faceof a semiconductor chip A as FIG. 2 shows.

Thus, a damaged layer 3 a (gettering layer) having grooves 3 b can beformed on the back face of a semiconductor chip A. Thereby, a getteringlayer having a uniform convexo-concave pattern can be formed.

FIG. 3 is a micrograph of the back face of a semiconductor chip A afterpolishing using the above-described method (refer to FIG. 2). Lineargrooves 3 b have been formed on the back face of a semiconductor chip A.

The damaged layer 3 a shown in FIG. 2 can also be formed by grindingusing grinding tools, such as a diamond wheel, sand blast, file, andneedle. Alternatively, the damaged layer 3 a can be formed using laserbeams or focused ion beams (FIB). Thereby, the damaged layer 3 a can beformed using a simple method.

Here, if the back face of a wafer or a semiconductor chip is ground toreduce thickness before assembling an MCP, there is a possibility thatthe gettering layer previously formed inside or on the back face of thewafer in the first-half process is lost or thinned. In addition, thethinner the thickness of a semiconductor chip, the more sensitive to theeffect of heavy-metal contamination of the back face.

However, as shown in this embodiment, by forming a gettering layer 3 onthe back face of a semiconductor chip A, heavy metals can be gettered inthe second-half process even if the thickness of the semiconductor chipA is thinned to 100 μm or less.

Next, the percent defectives of devices after assembling the MCP (thelower the percent defectives, the higher the yield of devices) werecompared when the gettering layer 3 was formed and not formed on theback face of the semiconductor chip A.

The results showed that when no gettering layer 3 was formed, thepercent defective of the device was 61%, whereas when a gettering layer3 was formed, the percent defective of the device was suppressed toabout 0.7%.

This is considered because heavy-metal contamination was suppressed, andthe percent defectives of devices caused by leakage current through thegate insulation film or the like were significantly lowered by thegettering layer 3.

As described above, in this embodiment, the gettering layer 3 formed onthe back face of the semiconductor chip A was a damaged layer 3 a.Thereby, heavy metals can be gettered in the second-half process.Therefore, the yield in the second-half process can be improved.

In this embodiment, the gettering layer 3 could be formed on the backface of the semiconductor chip A by forming the damaged layer 3 a bymechanically grinding the back face of the semiconductor chip A using asilica material. Thereby, the gettering layer having a uniformconvexo-concave pattern can be formed.

Alternatively, the gettering layer 3 could be formed on the back face ofthe semiconductor chip A using a simple method for forming the damagedlayer 3 a by grinding back face of the semiconductor chip A using agrinder.

Second Embodiment

In this embodiment, as an example of forming the gettering layer 3described in the first embodiment, an example of forming a damaged layerby ion implantation will be described.

FIG. 4 is a sectional view of a semiconductor chip A after a damagedlayer 3 c has been formed as the gettering layer 3 shown in FIG. 1 onthe back face of the semiconductor chip A by ion implantation. (In FIG.4, for the convenience of description, the back face of thesemiconductor chip A was upside.)

The damaged layer 3 c can be formed by ion implantation, for example,using ionic species, such as Ar⁺, P⁺, and BF₂, at an implanting energyof 50 to 100 keV or equivalent, and an implanting dose of 1×10¹³ to1×10¹⁴ atoms/cm².

Alternatively, by controlling the implanting energy or implanting doseof ion implantation, the density of crystal lattice defect can also becontrolled. Thereby, the gettering capacity can be improved as required.

In this embodiment, as described above, the gettering layer 3 formed onthe back face of the semiconductor chip A was a damaged layer 3 c formedon the back face of the semiconductor chip A by ion implantation.Thereby, in addition to the effect obtained in the first embodiment, thegettering capacity can be improved as required.

In this embodiment, a gettering layer 3 was formed on the back face ofthe semiconductor chip A by forming a damaged layer 3 c by implantingions into the back face of the semiconductor chip A. By thus forming, agettering layer having an improved gettering capacity as required becontrolling the implanting energy or implanting dose of ionimplantation.

Third Embodiment

In this embodiment, as an example of forming the gettering layer 3described in the first embodiment, an example of forming a thin filmwill be described.

FIG. 5 is a sectional view of a semiconductor chip A after forming athin film 3 d as a gettering layer 3 shown in FIG. 1 on the back face ofthe semiconductor chip A.

As the thin film 3 d, a polycrystalline silicon film or a siliconnitride film is formed by low-temperature CVD at, for example, about350° C. to 400° C. Thereby, the gettering layer can be formed by asimple method without affecting the characteristics of transistors andthe like.

The thickness of the thin film 3 d is about 1 μm, preferably within arange between, for example, 0.5 and 1.5 μm. This is because if the filmthickness is thinner than 0.5 μm, there is possibility that heavy metalscannot be sufficiently gettered; and if the film thickness is thickerthan 1.5 μm, there is possibility that defect is caused in thesecond-half process, such as poor bonding due to film stress.

By thus forming a thin film 3 d on the back face of the semiconductorchip A, a gettering layer having a uniform thickness can be formed.Thereby, uniform and stable gettering can be performed against heavymetals.

In this embodiment, as described above, the gettering layer 3 formed onthe back face of the semiconductor chip A was a thin film 3 d consistingof a polycrystalline silicon film or a silicon nitride film. Thereby, inaddition to the effect obtained by the first embodiment, uniform andstable gettering can be performed.

In this embodiment, a gettering layer 3 was formed on the back face ofthe semiconductor chip A by forming a thin film 3 d consisting of apolycrystalline silicon film or a silicon nitride film on the back faceof the semiconductor chip A. Thereby, a gettering layer 3 having auniform thickness can be formed.

Fourth Embodiment

In this embodiment, a semiconductor chip wherein an element layer havingtransistors and the like on the front face, and the back face is joinedto the underlying member such as an MCP substrate, wherein crystallattice defect is previously formed inside of the wafer before formingan element layer in the first-half process; and a method formanufacturing such a semiconductor chip.

FIG. 6 is a sectional view of a wafer B, after a crystal lattice defectlayer 4 has been formed inside the wafer B in the first-half process,then, forming an epitaxial layer 5 on the front face of the wafer B, andthen, forming an element layer 2 having transistors and the like on thefront face thereof. The wafer B is a p-type silicon wafer having aresistivity of 10 to 15 mΩ·cm due to the addition of boron, and a totalthickness T₁ of 700 to 750 μm.

Next, a method for forming a crystal lattice defect layer 4 and anepitaxial layer 5 shown in FIG. 6 will be described.

First, by a first heat treatment, a crystal lattice defect layer 4 isformed at the location of a depth T2 (about 50 to 80 μm) from the frontface of a wafer B. The first heat treatment is performed in a nitrogengas or argon gas atmosphere having a 2-step treatment wherein after heattreatment at 500 to 600° C. for 1 to 2 hours, heat treatment isperformed at 900 to 1000° C. for 2 to 3 hours. At this time, thetemperature and treating time in each step are controlled so that thedensity of crystal defect formed inside the wafer B becomes 1×10⁴/cm² ormore.

Next, by a second heat treatment, an epitaxial layer 5 of a thickness ofabout 5 to 10 μm is formed on the front face of the wafer B. The secondheat treatment is performed in a mixed-gas atmosphere of SiH₄(monosilane) and hydrogen at 1100 to 1150° C. for about 10 minutes.Thereby, the epitaxial layer 5 having a resistivity of 2 to 20 mΩ cm isformed on the front face of the wafer B. Furthermore, an element layer 2of a thickness of about 2 to 3 μm having transistors and the like isformed on the surface of the epitaxial layer 5.

Thereafter, a semiconductor chip of a thickness of about 90 μm (notshown) is formed by dicing the wafer B. At this time, since the crystallattice defect layer 4 has been formed at the location about 50 to 80 μmfrom the front face of the wafer B, the density of the crystal latticedefects contained in the entire semiconductor chip is 1×10⁴/cm² or moreeven after dicing.

Thus, a crystal lattice defect layer having a density of the crystallattice defects of 1×10⁴/cm² or more was previously formed inside thewafer B before forming the element layer so that the density of thecrystal lattice defects contained in the entire semiconductor chipfinally formed became 1×10⁴/cm² or more.

FIG. 7A is a micrograph of the wafer after above-described first andsecond heat treatments; and FIG. 7B is a micrograph of the wafer withouteither heat treatment (prior art).

By the comparison of both wafers, it is seen that a crystal latticedefect layer having a convexo-concave pattern formed by heat treatmentsis formed inside the wafer B. The density of the crystal lattice defectsof the wafer shown in FIG. 7A is 5.1×10⁶/cm².

Here, by performing heat treatment in an argon or hydrogen atmosphere at1200 to 1300° C. instead of the step for forming the epitaxial layer 5by the above-described second heat treatment, a non-defect layer (notshown) of a thickness of 5 to 20 μm can be formed on the front surfaceof wafer B.

FIG. 8A is a micrograph of the wafer after the above-described firstheat treatment and the heat treatment for forming the non-defect layer;and FIG. 8B is a micrograph of the wafer without either heat treatment(prior art).

By the comparison of both wafers, it is seen that a crystal latticedefect layer having a convexo-concave pattern formed by heat treatmentsis formed inside the wafer B. The density of the crystal lattice defectsof the wafer shown in FIG. 8A is 4.5×10⁵/cm².

Thus, in the first-half process, a crystal lattice defect layer isformed at the location about 50 to 80 μm from the front face inside thewafer so that the density of crystal lattice defects contained in theentire wafer becomes 1×10⁴/cm² or more. Thereby, even after the waferhas been diced to form a semiconductor chip having a thickness of 100 μmor less, a semiconductor chip having a density of crystal latticedefects contained in the entire semiconductor chip of 1×10⁴/cm² or morecan be obtained.

The percentage defect of the device after assembling an MCP using thissemiconductor chip was substantially equivalent to the percentage defectof the device (0.5%) when a gettering layer was formed on the back faceof the semiconductor chip.

This is considered because the crystal lattice defects contained in thesemiconductor chip has a gettering effect in the second-half process.

In this embodiment, before forming an element layer in the first-halfprocess, crystal lattice defects were previously formed inside the waferso that the density of crystal lattice defects contained in thesemiconductor chip finally formed became 1×10⁴/cm² or more. In additionto this, a gettering layer may be formed on the back face of thesemiconductor chip using the method shown in any of embodiments 1 to 3.Thereby, since the gettering effect in the second-half process isimproved, the yield of devices in the second-half process can be furtherimproved.

In this embodiment, as described above, after forming a crystal latticedefect layer 4 by the heat treatment of a wafer B so that the density ofcrystal lattice defects contained in the wafer became 1×10⁴/cm² or more,an element layer 2 was formed and the wafer B was diced to form asemiconductor chip having a density of crystal lattice defects of1×10⁴/cm² or more.

The semiconductor chip was thus formed so that a crystal lattice defectlayer is contained inside the semiconductor chip, and the density ofcrystal lattice defects contained in the entire semiconductor chipbecame 1×10⁴/cm² or more.

By this forming, the yield in the second-half process can also beimproved.

Fifth Embodiment

In this embodiment, there will be described a method for improving theyield of devices when a plurality of semiconductor chips are laminatedin the step for assembling an MCP. In the MCP, although three or moresemiconductor chips can be laminated on a substrate of the package,here, to simplify the description, an example wherein two semiconductorchips are laminated will be chiefly described.

FIG. 9 is a sectional view of an MCP formed by laminating twosemiconductor chips having two different thicknesses. An MCP substrate 7is fixed on solder balls 6, and a resin 8 is encapsulated inside theentire MCP. A lower semiconductor chip 10 is fixed on the MCP substrate7 through an adhesive layer 9. Further thereon, an upper semiconductorchip 12 is laminated through adhesive layers 9 and a spacer 11. Wiringterminals 13 a and 13 b are installed on the lower semiconductor chip 10and the upper semiconductor chip 12, respectively, which are connectedto wiring terminals 15 a and 15 b on the MCP substrate 7 by gold wires14 a and 14 b, respectively.

At this time, the lower semiconductor chip on the MCP substrate 7 islaminated so that the thickness thereof is relatively larger than thethickness of the upper semiconductor chip laminated immediately aboveit. In other words, in the MCP shown in FIG. 9, when the thickness ofthe upper semiconductor chip 12 is X μm, and the thickness of the lowersemiconductor chip 10 is Y μm, the relation is X<Y.

When three or more semiconductor chips are laminated in an MCP, thethickness of the semiconductor chip fixed on the substrate of the MCP ismade relatively larger than the thickness of the semiconductor chipfixed immediately above it.

By the above-described method, the percentage defects of devices werecompared in the step for assembling two semiconductor chips havingdifferent thicknesses into an MCP.

In FIG. 9, when the thickness of the upper semiconductor chip 12, X=150μm, and the thickness of the lower semiconductor chip 10, Y=90 μm (X>Y),the percentage defect of the device was 62.5%. Whereas, when X=90 μm andY=150 μm (X<Y), the percentage defect of the device was 1.2%, and thepercentage defect of the device could be significantly lowered.

This is considered because when the thickness of the lower semiconductorchip is relatively larger than thickness of the upper semiconductorchip, the stress imparted by the upper semiconductor chip to the lowersemiconductor chip can be relaxed. Thereby, the yield of devices in thestep for assembling the MCP can be improved.

In addition, as FIG. 9 shows, a silicon substrate or a polycrystallinesilicon film was laminated as a spacer 11 (cushioning material) betweenthe lower semiconductor chip 10 on the MCP substrate 7 and the uppersemiconductor chip 12 laminated immediately above it. For example, athin film formed by recovering and polishing a P-type silicon substratecontaining a P-type impurity, such as boron, or a dummy wafer containingan N-type silicon substrate consisting of an N-type impurity, such asphosphorus, so that the resistivity becomes 1 to 100 Ωcm, is used.Alternatively, a polycrystalline silicon film having a resistivity of 1to 100 Ωcm is used. Thereby, since the spacer 11 can getter heavy metalsin the step for assembling the MCP, the yield of devices in this stepcan be further improved.

In order to raise the integration degree of devices including the entirepackage, it is preferred to reduce the thickness of the entire MCP.Therefore, the above-described spacer 11 is preferably formed to bethin. However, if the spacer 11 is excessively thin, the getteringeffect is reduced; therefore, the spacer 11 is formed so as to have afilm thickness of 50 to 100 μm.

Since the spacer 11 acts as a cushioning material between the lowersemiconductor chip 10 and the upper semiconductor chip 12, the stressimparted by the upper semiconductor chip 12 to the lower semiconductorchip 10 can be relaxed. Thereby, the yield of devices in the step forassembling the MCP can be further improved.

As a semiconductor chip mounted in the MCP, a semiconductor chip havinga gettering layer formed on the back face shown in the first to fourthembodiments, or a semiconductor chip having a density of crystal latticedefect contained inside the semiconductor chip of 1×10⁴/cm² or more canalso be used. By using such a semiconductor chip, since the getteringeffect in the second-half process is improved, the yield of devices inthe step for assembling the MCP can be further improved.

In this embodiment, as described above, in a semiconductor packageformed by laminating a plurality of semiconductor chips on an MCPsubstrate 7, the thickness of the lower semiconductor chip on the MCPsubstrate 7 was relatively larger than the thickness of the uppersemiconductor chip laminated immediately above it. Thereby, the stressimparted by the upper semiconductor chip to the lower semiconductor chipcan be relaxed, and the yield of devices in the step for assembling theMCP can be improved.

1. A method for manufacturing a semiconductor package, comprising:forming an element layer on a front face of a semiconductor wafer, theelement layer including a transistor; dicing the semiconductor wafer soas to form a first semiconductor chip, after forming the element layer;polishing a back face of the first semiconductor chip so as to form agetting layer on the back face, after dicing the semiconductor wafer;and assembling a semiconductor package which includes a packagesubstrate, a second semiconductor chip formed over the packagesubstrate, the first semiconductor chip being formed over the secondsemiconductor chip, after polishing the back face of the firstsemiconductor chip, wherein the semiconductor package includes thegettering layer, the gettering layer is a damaged layer; the damagedlayer includes a plurality of grooves, a thickness of the firstsemiconductor chip is thinner than a thickness of the secondsemiconductor chip, and in plan view to said first semiconductor chip,each of the grooves is a linear groove.
 2. The method for manufacturingthe semiconductor package according to claim 1, wherein thesemiconductor package includes resin and a spacer, the methodcomprising: covering the first and second semiconductor chips and afront face of the package substrate with the resin, and arranging thespacer between the first semiconductor chip and the second semiconductorchip.
 3. The method for manufacturing the semiconductor packageaccording to claim 2, wherein: the spacer is a silicon substrate or apolysilicon film, a back face of the second semiconductor chip includesa gettering layer, and the semiconductor package includes a first wireand a second wire, the method comprising: electrically coupling thefirst semiconductor chip to the package substrate via the first wire,and electrically coupling the second semiconductor chip to the packagesubstrate via the second wire.
 4. A method for manufacturing asemiconductor package, comprising: forming an element layer on a frontface of a semiconductor wafer, the element layer including a transistor;dicing the semiconductor wafer so as to form a first semiconductor chip,after forming the element layer; polishing a back face of the firstsemiconductor chip so as to form a getting layer on the back face, afterdicing the semiconductor wafer; and assembling a semiconductor packagewhich includes a package substrate, the first semiconductor chip beingformed over the package substrate, after polishing the back face of thefirst semiconductor chip, wherein the semiconductor package includes thegettering layer, the gettering layer is a damaged layer, the damagedlayer includes a plurality of grooves, a depth of each of the grooves is2 to 3 μm, and in a plan view to said first semiconductor chip, each ofthe grooves is a linear groove.
 5. The method for manufacturing thesemiconductor package according to claim 4, comprising covering thefirst semiconductor chip and a front face of the package substrate witha resin.
 6. The method for manufacturing the semiconductor packageaccording to claim 5, wherein the semiconductor package includes a firstwire, the method comprising electrically coupling the firstsemiconductor chip to the package substrate via the first wire.